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| CY7C603xx enCoReTM III Low Voltage Features * Powerful Harvard Architecture Processor -- M8C Processor Speeds to 12 MHz -- Low Power at High Speed -- 2.4V to 3.6V Operating Voltage -- Operating Voltages Down to 1.0V Using On-Chip Switch Mode Pump (SMP) -- Commercial Temperature Range: 0C to +70C * Configurable Peripherals -- 8-bit Timers/Counters/PWM -- Full Duplex Master or Slave SPI -- 10-bit ADC -- 8-bit Successive Approximation ADC -- Comparator * Flexible On-Chip Memory -- 8K Flash Program Storage 50,000 Erase/Write Cycles -- 512 Bytes SRAM Data Storage -- In-System Serial Programming (ISSP) -- Partial Flash Updates -- Flexible Protection Modes -- EEPROM Emulation in Flash * Complete Development Tools -- Free Development Software (PSoC DesignerTM) -- Full-Featured, In-Circuit Emulator and Programmer -- Complex Breakpoint Structure -- 128K Trace Memory * Precision, Programmable Clocking -- Internal 2.5% 24-/48-MHz Oscillator -- Internal Oscillator for Watchdog and Sleep * Programmable Pin Configurations -- 10 mA Drive on All GPIO -- Pull-up, Pull-down, High Z, Strong, or Open Drain Drive Modes on All GPIO -- Up to 8 Analog Inputs on GPIO -- Configurable Interrupt on All GPIO * Versatile Analog Mux -- Common Internal Analog Bus -- Simultaneous Connection of IO Combinations * Additional System Resources -- I2C Master, Slave and Multi-Master to 400 kHz -- Watchdog and Sleep Timers -- User-Configurable Low Voltage Detection -- Integrated Supervisory Circuit -- On-Chip Precision Voltage Reference Cypress Semiconductor Corporation Document #: 38-16018 Rev. *D * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised October 10, 2006 [+] Feedback CY7C603xx Figure 1. enCoRe III Low Voltage Block Diagram Port 3 Port 2 Port 1 Port 0 System Bus Global Digital Interconnect SRAM 512 Bytes Interrupt Controller SROM Global Analog Interconnect Flash 8K Sleep and Watchdog CPU Core (M8C) Clock Sources (Includes IMO and ILO) enCoRe II LV Core DIGITAL SYSTEM Digital PSoC Block Array ANALOG SYSTEM Analog PSoC Block Array Analog Ref. Digital Clocks POR and LVD I2C System Resets Switch Mode Pump Internal Voltage Ref. Analog Mux SYSTEM RESOURCES Applications * * * * * * * Wireless mice Wireless gamepads Wireless Presenter tools Wireless keypads PlayStation(R) 2 wired gamepads PlayStation 2 bridges for wireless gamepads Applications requiring a cost effective low voltage 8-bit microcontroller. enCoRe III LV architecture, as illustrated in Figure 1, is composed of four main areas: the enCoRe III LV Core, the System Resources, Digital System, Analog System and System Resources. Configurable global bus resources allow all the device resources to be combined into a complete custom system. Each enCoRe III LV device supports a limited set of digital and analog peripherals. Depending on the package, up to 28 general purpose IOs (GPIOs) are also included. The GPIOs provide access to the global digital and analog interconnects. enCoRe III LV Core The enCoRe III LV core is a powerful engine that supports a rich feature set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO (internal main oscillator) and ILO (internal low-speed oscillator). The CPU core, called the M8C, is a powerful processor with speeds up to 12 MHz. The M8C is a four MIPS 8-bit Harvard architecture microprocessor. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO). System Resources provide additional capability, such as digital clocks to increase flexibility, I2C functionality for implementing an I2C master, slave, MultiMaster, an internal voltage reference that provides an absolute value of 1.3V to a number of subsystems, a switch mode pump (SMP) that generates Page 2 of 29 enCoRe III Low Voltage Functional Overview The enCoRe III Low Voltage (enCoRe III LV) CY7C603xx device is based on the flexible PSoC(R) architecture. A simple set of peripherals is supported that can be configured as required to match the needs of each application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts. This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in both a 28-pin SSOP and 32-pin QFN packages. Document #: 38-16018 Rev. *D [+] Feedback CY7C603xx normal operating voltages off a single battery cell, and various system resets supported by the M8C. The Digital System The Digital System is composed of 4 digital enCoRe III LV blocks. Each block is an 8-bit resource. Digital peripheral configurations include those listed below. * PWM usable as Timer/Counter * SPI master and slave * I2C slave and multi-master * CMP * ADC10 * SARADC Figure 2. Digital System Block Diagram Analog blocks are provided in columns of two, which includes one CT (Continuous Time - ACE00 or ACE01) and one SC (Switched Capacitor - ASE10 or ASE11) blocks. Figure 3. Analog System Block Diagram Array Input Configuration ACI0[1:0] AllIO ACI1[1:0] Port 3 Port 2 Port 1 Port 0 X X X ACOL1MUX Analog Mux Bus Digital Clocks From Core To System Bus To Analog System X X Array ACE00 ACE01 DIGITAL SYSTEM Digital enCoRe II LV Block Array Row 0 DBB00 DBB01 DCB02 ASE10 Row Output Configuration ASE11 Row Input Configuration 4 DCB03 4 8 8 8 8 The Analog Multiplexer System The Analog Mux Bus can connect to every GPIO pin. Pins can be connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with comparators and analog-to-digital converters. An additional 8:1 analog input multiplexer provides a second path to bring Port 0 pins to the analog array. Additional System Resources GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. The Analog System The Analog System is composed of two configurable blocks. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the common analog functions for this device (most available as user modules) are listed below. * Analog-to-digital converters (single with 8-bit resolution) * Pin-to-pin comparators * Single-ended comparators with absolute (1.3V) reference * 1.3V reference (as a System Resource) System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include a switch mode pump, low voltage detection, and power on reset. Brief statements describing the merits of each system resource are presented below. * Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital blocks as clock dividers. * The I2C module provides 100- and 400-kHz communication over two wires. Slave, master, and multi-master modes are all supported. * Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. Page 3 of 29 Document #: 38-16018 Rev. *D [+] Feedback CY7C603xx * An internal 1.3 voltage reference provides an absolute reference for the analog system. * An integrated switch mode pump (SMP) generates normal operating voltages from a single 1.2V battery cell, providing a low-cost boost converter. * Versatile analog multiplexer system. integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs. PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family. Figure 4. PSoC Designer Subsystems enCoRe III LV Device Characteristics enCoRe III LV devices have four digital blocks and four analog blocks. The following table lists the resources available for specific enCoRe III LV devices. Analog Columns Analog Blocks Analog Outputs Analog Inputs Digital Blocks Digital IO Digital Rows SRAM Size Flash Size PSoCTM Designer Graphical Designer Interface Context Sensitive Help Commands Results Part Number CY7C60323 -PVXC CY7C60323 -LFXC CY7C60333 -LFXC 24 28 28 1 1 1 4 4 4 24 28 26 0 0 0 2 2 2 4 4 4 512 Bytes 512 Bytes 512 Bytes 8K 8K 8K Importable Design Database Device Database Application Database Project Database User Modules Library PSoC Configuration Sheet Getting Started The quickest path to understanding the enCoRe III LV silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the enCoRe III LV and presents specific pin, register, and electrical specifications. enCoRe III LV is based on the architecture of the CY8C21x34. For in-depth information, along with detailed programming information, refer to the PSoC Mixed-Signal Array Technical Reference Manual, which can be found on http://www.cypress.com/psoc. For up-to-date Ordering, Packaging, and Electrical Specification information, refer to the latest device data sheets on the web at http://www.cypress.com. Development Kits Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for enCoRe III LV development. Go to the Cypress Online Store web site at http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click USB (Universal Serial Bus) to view a current list of available items. PSoCTM Designer Core Engine Manufacturing Information File Emulation Pod In-Circuit Emulator Device Programmer PSoC Designer Software Subsystems Device Editor The device editor subsystem allows the user to select different on-board analog and digital components called user modules using the blocks. Examples of user modules are ADCs, PWMs, and SPI. PSoC Designer sets up power-on initialization tables for selected block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the framework is generated, the user can add application-specific code to flesh out the framework. It is also possible to change the selected components and regenerate the framework. Development Tools PSoC Designer is a Microsoft(R) Windows(R)-based, integrated development environment for the enCoRe III LV. The PSoC Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (Refer to the PSoC Designer Functional Flow diagram below.) PSoC Designer helps the customer to select an operating configuration, write application code that uses the enCoRe III LV, and debug the application. This system provides design database management by project, an Document #: 38-16018 Rev. *D Page 4 of 29 [+] Feedback CY7C603xx Application Editor In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, compile, link, and build. Assembler. The macro assembler allows the assembly code to be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative mode and linked with other software modules to get absolute addressing. C Language Compiler. A C language compiler is available that supports the enCoRe III LV family of devices. Even if you have never worked in the C language before, the product quickly allows you to create complete C programs. The embedded, optimizing C compiler provides all the features of C tailored to the enCoRe III LV architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the device. Debugger commands allow the designer to read the program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. Hardware Tools In-Circuit Emulator A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and will operate with enCoRe III LV, enCoRe III, and all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the enCoRe III LV device in the target board and performs full speed (12 MHz) operation. Designing with User Modules The development process for the enCoRe III LV device differs from that of a traditional fixed-function microprocessor. The configurable analog and digital hardware blocks provide a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the IO pins. Iterative development cycles permit you to adapt the hardware as well as the software. This substantially lowers the risk of having to select a different part to meet the final design requirements. To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of prebuilt, pretested hardware peripheral functions, called "User Modules." User Modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The standard User Module library contains seven common peripherals such as ADCs, SPI, I2C and PWMs to configure the enCoRe III LV peripherals. Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures a digital enCoRe III LV block for 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides high-level functions to control and respond to hardware events at run time. The API also provides optional interrupt service routines that you can adapt as needed. The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. You pick the user modules you need for your project and map them onto the enCoRe III LV blocks with point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, you perform the "Generate Application" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions. Document #: 38-16018 Rev. *D Page 5 of 29 [+] Feedback CY7C603xx Figure 5. User Module and Source Code Development Flows Document Conventions Acronyms Used Device Editor User Module Selection Placement and Parameter -ization Source Code Generator Acronym AC ADC API CPU CT alternating current Description analog-to-digital converter application programming interface central processing unit continuous time external crystal oscillator Generate Application ECO Application Editor Project Manager Source Code Editor Build Manager EEPROM electrically erasable programmable read-only memory FSR GPIO GUI HBM ICE full scale range general purpose IO graphical user interface human body model in-circuit emulator internal low speed oscillator internal main oscillator input/output imprecise power on reset least-significant bit low voltage detect most-significant bit program counter phase-locked loop power on reset precision power on reset Programmable System-on-ChipTM pulse width modulator switched capacitor static random access memory Build All ILO IMO IO IPOR Debugger Interface to ICE Storage Inspector Event & Breakpoint Manager LSb LVD MSb PC PLL POR PPOR PSoC PWM SC SRAM The next step is to write your main program, and any subroutines using PSoC Designer's Application Editor subsystem. The Application Editor includes a Project Manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive "grep-style" patterns. A single mouse click invokes the Build Manager. It employs a professional-strength "makefile" system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a HEX file image suitable for programming. The last step in the development process takes place inside the PSoC Designer's Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. Units of Measure A units of measure table is located in the Electrical Specifications section. Table 5 on page 13 lists all the abbreviations used to measure the enCoRe III LV devices. Numeric Naming Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexidecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (e.g., 01010100b' or `01000011b'). Numbers not indicated by an `h' or `b' are decimal. Document #: 38-16018 Rev. *D Page 6 of 29 [+] Feedback CY7C603xx Packages/Pinouts The enCoRe III LV device is available in 28-pin SSOP and 32-pin QFN packages, which are listed and illustrated in the following tables. Every port pin (labeled with a "P") is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO. Table 1. 28-Pin Part Pinout (SSOP) Type Pin No. Digital Analog Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 IO IO IO IO IO IO IO IO IO IO IO IO Input I, M I, M M M I, M I, M I, M I, M Power IO IO IO IO Power M M M M IO IO IO IO IO IO IO IO I, M I, M I, M I, M M M I, M I, M Power M M M M P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] Vss P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES Active HIGH external reset with internal pull down. P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Analog column mux input. Analog column mux input. Analog column mux input Analog column mux input. Supply voltage. Direct switched capacitor block input. Direct switched capacitor block input. Optional External Clock Input (EXTCLK). I2C Serial Clock (SCL), ISSP-SCLK. Ground connection. I2C Serial Data (SDA), ISSP-SDATA. Direct switched capacitor block input. Direct switched capacitor block input. Ground connection. I2C Serial Clock (SCL). I2C Serial Data (SDA). CY7C60323-PVXC Device Description Analog column mux input. Analog column mux input and column output. Analog column mux input and column output, integrating input. Analog column mux input, integrating input. A, I, M, P0[7] A, I, M, P0[5] A, I, M, P0[3] A, I, M, P0[1] M, P2[7] M, P2[5] M, P2[3] M, P2[1] Vss M, I2C SCL, P1[7] M, I2C SDA, P1[5] M, P1[3] M, I2C SCL, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M P0[0], A, I, M P2[6], M P2[4], M P2[2], M P2[0], M XRES P1[6], M P1[4], EXTCLK, M P1[2], M P1[0], I2C SDA, M LEGEND A: Analog, I: Input, O = Output, and M = Analog Mux Input. Document #: 38-16018 Rev. *D Page 7 of 29 [+] Feedback CY7C603xx 32-Pin Part Pinout Table 2. 32-Pin Part Pinout (QFN*) A, I, M A, I, M A, I, M A, I, M P0[4], A, I, M P0[2], A, I, M 26 25 Type Pin No. Digital Analog Name 1 2 3 4 5 6 6 IO IO IO IO IO IO Power I, M M M M M M P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] SMP CY7C60323-LFXC Device Description Analog column mux input, integrating input. In CY7C60323 part. Switch Mode Pump (SMP) connection to required external components in CY7C60333 part. In CY7C60323 part. Ground connection in CY7C60333 part. I2C Serial Clock (SCL). I2C Serial Data (SDA). I2C Serial Clock (SCL), ISSP-SCLK. Ground connection. I2C Serial Data (SDA), ISSP-SDATA. 7 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 IO Power IO IO IO IO Power IO IO IO IO Input IO IO IO IO IO IO IO IO IO IO IO IO IO M M M M M M M M M P3[1] Vss P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] A, I, M, P0[1] M, P2[7] M, P2[5] M, P2[3] M, P2[1] M, P3[3] M, P3[1] M, I2C SCL, P1[7] 1 2 3 4 5 6 7 8 32 31 30 29 28 27 Vss P0[3], P0[5], P0[7], Vdd P0[6], QFN (Top View) M, I2C SDA, P1[5] M, P1[3] CY7C60333-LFXC Device A, I, M A, I, M A, I, M A, I, M P0[4], A, I, M P0[2], A, I, M 26 25 Optional External Clock Input (EXTCLK). M M M M M M I, M I, M I, M I, M Power I, M I, M I, M Power P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd P0[7] P0[5] P0[3] Vss Analog column mux input. Analog column mux input. Analog column mux input. Analog column mux input. Supply voltage. Analog column mux input. Analog column mux input. Analog column mux input, integrating input. Ground connection. A, I, M, P0[1] M, P2[7] M, P2[5] M, P2[3] M, P2[1] SMP Vss M, I2C SCL, P1[7] 1 2 3 4 5 6 7 8 32 31 30 29 28 27 Vss P0[3], P0[5], P0[7], Vdd P0[6], XRES Active HIGH external reset with internal pull down. M, I2C SCL, P1[1] Vss M, I2C SDA, P1[0] M, P1[2] M, EXTCLK, P1[4] M, P1[6] 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 P0[0], A, I, M P2[6], M P2[4], M P2[2], M P2[0], M P3[2], M P3[0], M XRES QFN (Top View) LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. * The QFN package has a center pad that must be connected to ground (Vss). Document #: 38-16018 Rev. *D M, I2C SDA, P1[5] M, P1[3] M, I2C SCL, P1[1] Vss M, I2C SDA, P1[0] M, P1[2] M, EXTCLK, M, P1[4] P1[6] 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 P0[0], A, I, M P2[6], M P2[4], M P2[2], M P2[0], M P3[2], M P3[0], M XRES Page 8 of 29 [+] Feedback CY7C603xx Register Reference This section lists the registers of the enCoRe III LV device. For detailed register information, reference the PSoC Mixed-Signal Array Technical Reference Manual. Register Conventions The register conventions specific to this section are listed in the following table. Convention R W L C # Description Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific Register Mapping Tables The enCoRe III LV device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1. Note: In the following register mapping tables, blank fields are Reserved and should not be accessed. Table 3. Register Map 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 Addr (0,Hex) Access 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D ASE11CR0 Access Name ASE10CR0 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D # Access is bit specific. INT_CLR3 IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 CUR_PP STK_PP RW Access RW Name Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD RW RW RW RW RW # RW # RW RW RW RW Access Blank fields are Reserved and should not be accessed. Document #: 38-16018 Rev. *D Page 9 of 29 [+] Feedback CY7C603xx Table 3. Register Map 0 Table: User Space (continued) Name Addr (0,Hex) Access 1E 1F DBB00DR0 DBB00DR1 DBB00DR2 DBB00CR0 DBB01DR0 DBB01DR1 DBB01DR2 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 DCB03DR1 DCB03DR2 DCB03CR0 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F ACE01CR1 ACE01CR2 ACE00CR1 ACE00CR2 # W RW # # W RW # # W RW # # W RW # TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ADC0_CR ADC1_CR CMP_CR1 CMP_CR0 AMX_IN AMUXCFG PWM_CR Name Addr (0,Hex) 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 # # RW # RW RW RW Access Name Addr (0,Hex) 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. DAC_D CPU_SCR1 CPU_SCR0 RW RW RW RW RW RW RW CPU_F DEC_CR0 DEC_CR1 INT_MSK0 INT_MSK1 INT_VC RES_WDT Access Name INT_MSK3 Addr (0,Hex) DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW # # RL RW RW RW RW RC W Access RW Blank fields are Reserved and should not be accessed. Document #: 38-16018 Rev. *D Page 10 of 29 [+] Feedback CY7C603xx Table 4. Register Map 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 Addr (1,Hex) Access 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBB00FN DBB00IN DBB00OU DBB01FN DBB01IN DBB01OU DCB02FN DCB02IN DCB02OU 20 21 22 23 24 25 26 27 28 29 2A 2B RW RW RW CLK_CR3 RW RW RW AMD_CR1 ALT_CR0 RW RW RW CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 65 66 67 68 69 6A 6B RW RW RW RW RW RW RW RW ASE11CR0 Access Name ASE10CR0 Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB # Access is bit specific. IMO_TR ILO_TR BDG_TR ECO_TR OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU RW Access RW Name Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC OSC_GO_EN DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB W W RW W RW RW RW RW RW RW RW R RW RW RW RW RW RW RW RW RW RW Access CMP_GO_EN 64 Blank fields are Reserved and should not be accessed. Document #: 38-16018 Rev. *D Page 11 of 29 [+] Feedback CY7C603xx Table 4. Register Map 1 Table: Configuration Space (continued) Name DCB03FN DCB03IN DCB03OU Addr (1,Hex) Access 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F ACE01CR1 ACE01CR2 ACE00CR1 ACE00CR2 RW RW RW Name TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 Addr (1,Hex) 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW Access RW RW RW RW RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 Name Addr (1,Hex) AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. DAC_CR CPU_SCR1 CPU_SCR0 FLS_PR1 RW RW RW RW RW RW RW CPU_F Access Name Addr (1,Hex) EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW # # RW RL Access Blank fields are Reserved and should not be accessed. Document #: 38-16018 Rev. *D Page 12 of 29 [+] Feedback CY7C603xx Electrical Specifications This section presents the DC and AC electrical specifications of the enCoRe III LV device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com Specifications are valid for 0C TA 70C and TJ 85C as specified, except where noted. Refer to Table 17 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode. Figure 6. Voltage versus CPU Frequency 3.60 V Vdd Voltage 3.60 V Figure 7. IMO Frequency Trim Options SLIMO Mode=1 SLIMO Mode=0 Vdd Voltage 3.00 V SLIMO SLIMO Mode=1 Mode=1 2.40 V 93 kHz 6 MHz 12 MHz 24 MHz IMO Frequency 3.00 V 2.70 V 2.40 V 93 kHz Valid Operating Region 3 MHz 12 MHz CPU Frequency The allowable CPU operating region for 12 MHz has been extended down to 2.7V from the original 3.0V design target. The customer's application is responsible for monitoring voltage and throttling back CPU speed in accordance with Figure 6 when voltage approaches 2.7V. Refer to Table 15 for LVD specifications. Note that the device does not support a preset trip at 2.7V. To detect Vdd drop at 2.7V, an external circuit or device such as the WirelessUSB LP - CYRF6936 must be employed; or if the design permits, the nearest LVD trip value at 2.9V can be used. Table 5 lists the units of measure that are used in this section. Table 5. Units of Measure Symbol C dB fF Hz KB Kbit kHz k MHz M A F H s V Vrms Unit of Measure degree Celsius decibels femtofarad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square Symbol W mA ms mV nA ns nV W pA pF pp ppm ps sps s V Unit of Measure microwatts milliampere millisecond millivolts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts Document #: 38-16018 Rev. *D Page 13 of 29 [+] Feedback CY7C603xx Absolute Maximum Ratings Table 6. Absolute Maximum Ratings Parameter Description TSTG Storage Temperature TA Vdd VIO VIOZ IMIO ESD LU Min. -40 Typ. - - - - - - - - Max. +90 +70 5 Vdd + 0.5 Vdd + 0.5 +25 - 200 Unit C C V V V mA V mA Notes Higher storage temperatures will reduce data retention time. Ambient Temperature with Power Applied 0 Supply Voltage on Vdd Relative to Vss -0.5 DC Input Voltage Vss - 0.5 DC Voltage Applied to Tri-state Vss - 0.5 Maximum Current into any Port Pin -25 Electro Static Discharge Voltage 2000 Latch-up Current - Human Body Model ESD. Operating Temperature Table 7. Operating Temperature Parameter TA TJ Description Ambient Temperature Junction Temperature Min. 0 0 Typ. - - Max. +70 +85 Unit C C The temperature rise from ambient to junction is package specific. See "Thermal Impedances" on page 27. The user must limit the power consumption to comply with this requirement. Notes DC Electrical Characteristics DC Chip-Level Specifications Table 8 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and 0C < TA < 70C, or 2.4V to 3.0V and 0C < TA < 70C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25C and are for design guidance only. Table 8. DC Chip-Level Specifications Parameter Description Vdd Supply Voltage IDD3 Supply Current, IMO = 6 MHz using SLIMO mode. Min. 2.40 - Typ. - 1.2 Max. 3.6 2 Unit Notes V See Table 15 on page 18. mA Conditions are Vdd = 3.3V, TA = 25C, CPU = 3 MHz, clock doubler disabled. VC1 = 375 kHz, VC2 = 23.4 kHz, VC3 = 0.091 kHz. mA Conditions are Vdd = 2.55V, TA = 25C, CPU = 3 MHz, clock doubler disabled. VC1 = 375 kHz, VC2 = 23.4 kHz, VC3 = 0.091 kHz. A Vdd = 2.55V, 0C < TA < 40C. A V V V IDD27 Supply Current, IMO = 6 MHz using SLIMO mode. - 1.1 1.5 ISB27 ISB VREF VREF27 AGND Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Mid temperature range. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Reference Voltage (Bandgap) Reference Voltage (Bandgap) Analog Ground - 2.6 4. - 1.28 1.16 2.8 1.30 1.30 5 1.32 1.33 Vdd = 3.3V, 0C < TA < 70C. Trimmed for appropriate Vdd. Vdd = 3.0V to 3.6V. Trimmed for appropriate Vdd. Vdd = 2.4V to 3.0V. VREF - VREF VREF + 0.003 0.003 Document #: 38-16018 Rev. *D Page 14 of 29 [+] Feedback CY7C603xx DC General Purpose IO Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and 0C < TA < 70C, or 2.4V to 3.0V and 0C < TA < 70C, respectively. Typical parameters apply to 3.3V, and 2.7V at 25C and are for design guidance only. Table 9. 3.3V DC GPIO Specifications Parameter RPU RPD VOH VOL VIL VIH VH IIL CIN COUT Description Pull-up Resistor Pull-down Resistor High Output Level Low Output Level Input Low Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output Min. 4 4 Vdd - 1.0 - - 2.1 - - - - Typ. 5.6 5.6 - - - - 60 1 3.5 3.5 - - 10 10 Max. 8 8 - 0.75 0.8 Unit k k V V V V mV nA pF pF Gross tested to 1 A. Package and pin dependent. Temp = 25C. Package and pin dependent. Temp = 25C. IOH = 3 mA, VDD > 3.0V IOL = 10 mA, VDD > 3.0V Vdd = 3.0 to 3.6. Vdd = 3.0 to 3.6. Notes Table 10.2.7V DC GPIO Specifications Parameter RPU RPD VOH Description Pull-up Resistor Pull-down Resistor High Output Level Min. 4 4 Vdd - 0.4 - - 2.0 - - - - Typ. 5.6 5.6 - Max. 8 8 - Unit k k V IOH = 2.5 mA (6.25 Typ), VDD = 2.4 to 3.0V (16 mA maximum, 50 mA Typ combined IOH budget). IOL = 10 mA, VDD = 2.4 to 3.0V (90 mA maximum combined IOL budget). Vdd = 2.4 to 3.0. Vdd = 2.4 to 3.0. Gross tested to 1 A. Package and pin dependent. Temp = 25C. Package and pin dependent. Temp = 25C. Notes VOL VIL VIH VH IIL CIN COUT Low Output Level Input Low Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output - - - 90 1 3.5 3.5 0.75 0.75 - - - 10 10 V V V mV nA pF pF Document #: 38-16018 Rev. *D Page 15 of 29 [+] Feedback CY7C603xx DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and 0C < TA < 70C, or 2.4V to 3.0V and 0C < TA < 70C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25C and are for design guidance only. Table 11.3.3V DC Operational Amplifier Specifications Parameter VOSOA TCVOSOA IEBOA[1] CINOA VCMOA GOLOA ISOA Description Input Offset Voltage (absolute value) Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Open Loop Gain Amplifier Supply Current Min. - - - - 0 - - Typ. 2.5 10 200 4.5 - 80 10 Max. 15 - - 9.5 Vdd - 1 - 30 Unit mV V/C pA pF V dB A Gross tested to 1 A. Package and pin dependent. Temp = 25C. Notes Table 12.2.7V DC Operational Amplifier Specifications Parameter VOSOA TCVOSOA IEBOA[1] CINOA VCMOA GOLOA ISOA Description Input Offset Voltage (absolute value) Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Open Loop Gain Amplifier Supply Current Min. - - - - 0 - - Typ. 2.5 10 200 4.5 - 80 10 Max. 15 - - 9.5 Vdd - 1 - 30 Unit mV V/C pA pF V dB A Gross tested to 1 A. Package and pin dependent. Temp = 25C. Notes Note 1. Atypical behavior: IEBOA of Port 0 Pin 0 is below 1 nA at 25C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA. Document #: 38-16018 Rev. *D Page 16 of 29 [+] Feedback CY7C603xx DC Switch Mode Pump Specifications Table 13 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and 0C < TA < 70C, or 2.4V to 3.0V and 0C < TA < 70C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25C and are for design guidance only. Table 13.DC Switch Mode Pump (SMP) Specifications Parameter VPUMP3V Description 3.3V Output Voltage from Pump Min. 3.00 Typ. 3.25 Max. 3.60 Unit Notes V Configuration of footnote.[2] Average, neglecting ripple. SMP trip voltage is set to 3.25V. V Configuration of footnote.[2] Average, neglecting ripple. SMP trip voltage is set to 2.55V. Configuration of footnote.[2] mA SMP trip voltage is set to 3.25V. mA SMP trip voltage is set to 2.55V. V Configuration of footnote.[2] SMP trip voltage is set to 3.25V. V Configuration of footnote.[2] SMP trip voltage is set to 2.55V. V Configuration of footnote.[2] 0C < TA < 100. 1.25V at TA = -40C. %VO Configuration of footnote.[2] VO is the "Vdd Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 15 on page 18. %VO Configuration of footnote.[2] VO is the "Vdd Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 15 on page 18. mVpp Configuration of footnote.[2] Load is 5 mA. % % Configuration of footnote.[2] Load is 5 mA. SMP trip voltage is set to 3.25V. For I load = 1 mA, VPUMP = 2.55V, VBAT = 1.3V, 10 H inductor, 1 F capacitor, and Schottky diode. VPUMP2V 2.6V Output Voltage from Pump 2.45 2.55 2.80 IPUMP VBAT3V VBAT2V VBATSTART VPUMP_Line Available Output Current VBAT = 1.5V, VPUMP = 3.25V VBAT = 1.3V, VPUMP = 2.55V Input Voltage Range from Battery Input Voltage Range from Battery Minimum Input Voltage from Battery to Start Pump Line Regulation (over Vi range) 8 8 1.0 1.0 1.2 - - - - - - 5 - - 3.3 2.8 - - VPUMP_Load Load Regulation - 5 - VPUMP_Ripple Output Voltage Ripple (depends on cap/load) E3 Efficiency E2 Efficiency - 35 35 100 50 80 - - - FPUMP DCPUMP Switching Frequency Switching Duty Cycle - - 1.3 50 - - MHz % Figure 8. Basic Switch Mode Pump Circuit D 1 Vdd VPUMP L1 VBAT enCoRe III LV SMP C 1 + Battery Vss Note 2. L1 = 2 H inductor, C1 = 10 F capacitor, D1 = Schottky diode. See Figure 8. Page 17 of 29 Document #: 38-16018 Rev. *D [+] Feedback CY7C603xx DC Analog Mux Bus Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and 0C < TA < 70C, or 2.4V to 3.0V and 0C < TA < 70C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25C and are for design guidance only. Table 14.DC Analog Mux Bus Specifications Parameter Description RSW Switch Resistance to Common Analog Bus RVDD Resistance of Initialization Switch to Vdd Min. - - Typ. - - Max. 400 800 800 Unit Notes Vdd > 2.7V 2.4V < Vdd < 2.7V DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and 0C < TA < 70C, or 2.4V to 3.0V and 00C < TA < 70C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25C and are for design guidance only. Table 15.DC POR and LVD Specifications Parameter VPPOR0 VPPOR1 VLVD0 VLVD1 VLVD2 VLVD37 VPUMP0 VPUMP1 VPUMP2 VPUMP3 Description Vdd Value for PPOR Trip PORLEV[1:0] = 00b PORLEV[1:0] = 01b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b Vdd Value for PUMP Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b 2.45 2.96 3.03 3.18 2.55 3.02 3.10 3.25 2.62[5] 3.09 3.16 3.32[6] V V V V 2.40 2.85 2.95 3.06 2.45 2.92 3.02 3.13 2.51[3] 2.99[4] 3.09 3.20 V V V V Min. Typ. 2.36 2.82 Max. 2.40 2.95 Unit V V Notes Vdd must be greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from Watchdog. - Notes 3. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply. 4. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply. 5. Always greater than 50 mV above VLVD0. 6. Always greater than 50 mV above VLVD3. Document #: 38-16018 Rev. *D Page 18 of 29 [+] Feedback CY7C603xx DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and 0C < TA < 70C, or 2.4V to 3.0V and 0C < TA < 70C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25C and are for design guidance only. Table 16.DC Programming Specifications Parameter IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENT FlashDR Description Supply Current During Programming or Verify Input Low Voltage During Programming or Verify Input High Voltage During Programming or Verify Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify Output Low Voltage During Programming or Verify Output High Voltage During Programming or Verify Flash Endurance (total)[7] Flash Data Retention Min. 2.70 - - 2.1 - - - Vdd - 1.0 50,000 1,800,000 10 Typ. Max. - 5 - - - - - - - - - - 25 0.8 - 0.2 1.5 Vss + 0.75 Vdd - - - Unit V mA V V mA Driving internal pull down resistor. mA Driving internal pull down resistor. V V - - Years Erase/write cycles per block. Erase/write cycles. Notes VddIWRITE Supply Voltage for Flash Write Operations FlashENPB Flash Endurance (per block) Note 7. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). Document #: 38-16018 Rev. *D Page 19 of 29 [+] Feedback CY7C603xx AC Electrical Characteristics AC Chip-Level Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and 0C < TA < 70C, or 2.4V to 3.0V and 0C < TA < 70C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25C and are for design guidance only. Table 17.3.3V AC Chip-Level Specifications Parameter Description FIMO24 Internal Main Oscillator Frequency for 24 MHz FIMO6 Internal Main Oscillator Frequency for 6 MHz Min. 23.4 Max. Unit Notes 24.6[8, 9] MHz Trimmed for 3.3V operation using factory trim values. See Figure 7 on page 13. SLIMO mode = 0. 6 6.35[8, 9] MHz Trimmed for 3.3V operation using factory trim values. See Figure 7 on page 13. SLIMO mode = 1. 12 12.3[8, 9] MHz 24 24.6[8, 10] MHz 32 64 kHz 100 200 ns 1400 - - - s 50 60 % 50 - kHz 48.0 49.2[9] MHz Trimmed. Using factory trim values. 600 ps - 12.3 MHz - - s Typ. 24 5.75 FCPU2 FBLK33 F32K1 Jitter32k Jitter32k TXRST DC24M Step24M Fout48M Jitter24M1 FMAX TRAMP CPU Frequency (3.3V Nominal) 0.93 Digital Block Frequency (3.3V Nominal) 0 Internal Low Speed Oscillator Frequency 15 32 kHz RMS Period Jitter - 32 kHz Peak-to-Peak Period Jitter - External Reset Pulse Width 10 24 MHz Duty Cycle 40 24 MHz Trim Step Size - 48 MHz Output Frequency 46.8 24 MHz Peak-to-Peak Period Jitter (IMO) - Maximum frequency of signal on row - input or row output. Supply Ramp Time 0 Table 18.2.7V AC Chip-Level Specifications Parameter Description FIMO12 Internal Main Oscillator Frequency for 12 MHz Min. 11.5 Typ. 120 Max. 12.7[8, 11] Unit MHz Notes Trimmed for 2.7V operation using factory trim values. See Figure 7 on page 13. SLIMO mode = 1. Trimmed for 2.7V operation using factory trim values. See Figure 7 on page 13. SLIMO mode = 1. 24 MHz only for SLIMO mode = 0. Refer to the AC Digital Block Specifications below. FIMO6 Internal Main Oscillator Frequency for 6 MHz 5.75 6 6.35[8, 11] MHz FCPU1 FBLK27 F32K1 Jitter32k Jitter32k TXRST FMAX TRAMP CPU Frequency (2.7V Nominal) Digital Block Frequency (2.7V Nominal) Internal Low Speed Oscillator Frequency 32 kHz RMS Period Jitter 32 kHz Peak-to-Peak Period Jitter External Reset Pulse Width Maximum frequency of signal on row input or row output. Supply Ramp Time 0.093 0 8 - - 10 - 0 3 12 32 150 1400 - - - 3.15[8, 11] 12.5[8, 11] 96 200 - - 12.3 - MHz MHz kHz ns s MHz s Notes 8. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 9. 3.0V < Vdd < 3.6V. 10. See the individual user module data sheets for information on maximum frequencies for user modules. 11. 2.4V < Vdd < 3.0V. Document #: 38-16018 Rev. *D Page 20 of 29 [+] Feedback CY7C603xx Figure 9. 24-MHz Period Jitter (IMO) Timing Diagram Jitter24M1 F24M Figure 10. 32-kHz Period Jitter (ILO) Timing Diagram Jitter32k F32K1 AC General Purpose IO Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and 0C < TA < 70C, or 2.4V to 3.0V and 0C < TA < 70C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25C and are for design guidance only. Table 19.3.3V AC GPIO Specifications Parameter FGPIO TRiseS TFallS Description GPIO Operating Frequency Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF Min. 0 7 7 Typ. - 27 22 Max. 12 - - Unit MHz ns ns Notes Normal Strong Mode Vdd = 3 to 3.6V, 10%-90% Vdd = 3 to 3.6V, 10%-90% Table 20.2.7V AC GPIO Specifications Parameter FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF Min. 0 6 6 18 18 Typ. - - - 40 40 Max. 3 50 50 120 120 Unit MHz ns ns ns ns Notes Normal Strong Mode Vdd = 2.4 to 3.0V, 10%-90% Vdd = 2.4 to 3.0V, 10%-90% Vdd = 2.4 to 3.0V, 10%-90% Vdd = 2.4 to 3.0V, 10%-90% Figure 11. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS Document #: 38-16018 Rev. *D Page 21 of 29 [+] Feedback CY7C603xx AC Operational Amplifier Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and 0C < TA < 70C, or 2.4V to 3.0V and 0C < TA < 70C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25C and are for design guidance only. Table 21.AC Operational Amplifier Specifications Parameter TCOMP Description Comparator Mode Response Time, 50 mV Overdrive Min. Typ. Max. 100 200 Unit ns ns Notes Vdd > 3.0V. 2.4V < Vcc < 3.0V. AC Analog Mux Bus Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and 0C < TA < 70C, or 2.4V to 3.0V and 0C < TA < 70C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25C and are for design guidance only. Table 22.AC Analog Mux Bus Specifications Parameter FSW Switch Rate Description Min. - Typ. - Max. 3.17 Unit MHz Notes AC Digital Block Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and 0C < TA < 70C, or 2.4V to 3.0V and 0C < TA < 70C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25C and are for design guidance only. Table 23.3.3V AC Digital Block Specifications Function Timer/ Counter/ PWM Dead Band Description Enable Pulse Width Maximum Frequency Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency SPIM SPIS Transmitter Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions Maximum Input Clock Frequency Maximum Input Clock Frequency 20 50 50 - - - 50 - - - - - - - - - - - - - - 49.2 8.2 4.1 - 24.6 24.6 ns ns ns MHz MHz MHz ns MHz MHz Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 3.08 MHz due to 8 x over clocking. 4.75V < Vdd < 5.25V. Maximum data rate at 4.1 MHz due to 2 x over clocking. Min. 50[12] - Typ. - - Max. 24.6 - 24.6 Unit MHz ns MHz Notes 3.0V < Vdd < 3.6V. All Functions Maximum Block Clocking Frequency (< 3.6V) Note 12. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period). Document #: 38-16018 Rev. *D Page 22 of 29 [+] Feedback CY7C603xx AC External Clock Specifications Table 24.2.7V AC Digital Block Specifications Function Timer/ Counter/ PWM Dead Band Description Enable Pulse Width Maximum Frequency Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency SPIM SPIS Transmitter Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions Maximum Input Clock Frequency Maximum Input Clock Frequency 20 100 100 - - - 100 - - - - - - - - - - - - - - 12.7 6.35 4.1 - 12.7 12.7 ns ns ns MHz MHz Maximum data rate at 3.17 MHz due to 2 x over clocking. MHz ns MHz Maximum data rate at 1.59 MHz due to 8 x over clocking. MHz Maximum data rate at 1.59 MHz due to 8 x over clocking. Min. 100 - Typ. - - Max. 12.7 - 12.7 Unit ns MHz Notes All Functions Maximum Block Clocking Frequency MHz 2.4V < Vdd < 3.0V. The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and 0C < TA < 70C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25C and are for design guidance only. Table 25.3.3V AC External Clock Specifications Parameter FOSCEXT Description Frequency with CPU Clock divide by 1 Min. 0.093 Typ. Max. Unit - Notes 12.3 MHz Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. 24.6 MHz If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met. 5300 - - ns ns s FOSCEXT Frequency with CPU Clock divide by 2 or 0.186 greater - - - - High Period with CPU Clock divide by 1 Low Period with CPU Clock divide by 1 Power Up IMO to Switch 41.7 41.7 150 - - - Document #: 38-16018 Rev. *D Page 23 of 29 [+] Feedback CY7C603xx Table 26.2.7V AC External Clock Specifications Parameter FOSCEXT Description Frequency with CPU Clock divide by 1 Min. 0.093 Typ. Max. - 3.08 0 Unit Notes MHz Maximum CPU frequency is 3 MHz at 2.7V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. MHz If the frequency of the external clock is greater than 3 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met. ns ns s FOSCEXT Frequency with CPU Clock divide by 2 or 0.186 greater - 6.35 - - - High Period with CPU Clock divide by 1 Low Period with CPU Clock divide by 1 Power Up IMO to Switch 160 160 150 - - - 5300 - - AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and 0C < TA < 70C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25C and are for design guidance only. Table 27.AC Programming Specifications Parameter TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK3 TDSCLK2 Description Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Min. 1 1 40 40 0 - - - - Typ. - - - - - 15 30 - - Max. 20 20 - - 8 - - 50 70 Unit ns ns ns ns MHz ms ms ns ns 3.0 Vdd 3.6 2.4 Vdd 3.0 Notes Document #: 38-16018 Rev. *D Page 24 of 29 [+] Feedback CY7C603xx AC I2C Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and 0C < TA < 70C, or 2.4V to 3.0V and 0C < TA < 70C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25C and are for design guidance only. Table 28.AC Characteristics of the I2C SDA and SCL Pins for Vdd > 3.0V Parameter FSCLI2C Description SCL Clock Frequency Standard Mode Min. 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 - Max. 100 - - - - - - - - - Fast Mode Min. 0 0.6 1.3 0.6 0.6 0 100[13] 0.6 1.3 0 Max. 400 - - - - - - - - 50 Unit kHz s s s s s ns s s ns Notes THDSTAI2C Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. TLOWI2C THIGHI2C TSUSTAI2C LOW Period of the SCL Clock HIGH Period of the SCL Clock Set-up Time for a Repeated START Condition THDDATI2C Data Hold Time TSUDATI2C Data Set-up Time TSUSTOI2C Set-up Time for STOP Condition TBUFI2C TSPI2C Bus Free Time Between a STOP and START Condition Pulse Width of spikes are suppressed by the input filter. Table 29.2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported) Parameter FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Description SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Set-up Time for a Repeated START Condition Data Hold Time Data Set-up Time Set-up Time for STOP Condition Bus Free Time Between a STOP and START Condition Pulse Width of spikes are suppressed by the input filter. Standard Mode Min. 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 - Max. 100 - - - - - - - - - Fast Mode Min. - - - - - - - - - - Max. - - - - - - - - - - Unit kHz s s s s s ns s s ns Notes Note 13. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT > 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document #: 38-16018 Rev. *D Page 25 of 29 [+] Feedback CY7C603xx Figure 12. Definition for Timing for Fast/Standard Mode on the I2C Bus SDA TLOWI2C TSUDATI2C THDSTAI2C TSPI2C TBUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C Sr P S Packaging Information This section illustrates the packaging specifications for the CY7C603xx device, along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/support/link.cfm?mr=poddim. Packaging Dimensions Figure 13. 28-Lead (210-Mil) SSOP 51-85079-*C Document #: 38-16018 Rev. *D Page 26 of 29 [+] Feedback CY7C603xx Figure 14. 32-Lead QFN (5 x 5 mm) DIMENSIONS IN mm MIN. MAX. 0.05 4.90 5.10 4.65 4.85 N 0.93 MAX. 0.05 MAX. 0.80 MAX. 0.20 REF. 3.70 0.230.05 N PIN1 ID 0.20 R. 0.45 1 2 4.90 5.10 C 1 2 0.50 DIA. 4.65 4.85 3.70 3.50 0-12 C SEATING PLANE 0.30-0.50 0.50 3.50 0.420.18 (4X) TOP VIEW SIDE VIEW BOTTOM VIEW JEDEC # MO-220 Package Weight: 0.054 grams 51-85188-*A Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. Thermal Impedances Table 30.Thermal Impedances per Package Package 28 SSOP 32 QFN * TJ = TA + Power x JA Typical JA * 96 C/W 22 C/W Typical JC 39 C/W 12 C/W Package 28 SSOP 32 QFN Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Table 31.Solder Reflow Peak Temperature Minimum Peak Temperature* 240C 240C Maximum Peak Temperature 260C 260C *Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 2205C with Sn-Pb or 2455C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. Document #: 38-16018 Rev. *D Page 27 of 29 [+] Feedback CY7C603xx Ordering Information The following table lists the CY7C603xx device's key package features and ordering codes. Table 32.CY7C603xx Device Key Features and Ordering Information Ordering Part Number CY7C60323-PVXC CY7C60323-PVXCT CY7C60323-LFXC CY7C60323-LFXCT CY7C60333-LFXC CY7C60333-LFXCT Flash Size 8K 8K 8K 8K 8K 8K RAM Size 512 512 512 512 512 512 SMP No No No No Yes Yes I/O 24 24 28 28 26 26 Package Type 28-SSOP 28-SSOP Tape and Reel 32-QFN 32-QFN Tape and Reel 32-QFN 32-QFN Tape and Reel PlayStation is a registered trademark of Sony. Microsoft and Windows are registered trademarks of Microsoft Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. PSoC is a registered trademark and enCoRe and Programmable System-on-Chip are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-16018 Rev. *D Page 28 of 29 (c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C603xx Document History Page Description Title: CY7C603xx, enCoReTM III Low Voltage Document Number: 38-16018 REV. ** *A ECN NO. 339394 399556 Issue Date See ECN See ECN Orig. of Change BON BHA Description of Change New Advance Data Sheet Changed from Advance Information to Preliminary. Changed data sheet format. Removed CY7C604xx. Modified Figure 6 to include 2.7V Vdd at 12-MHz operation Corrected part numbers in section 4 to match with part numbers in Ordering Information. From CY7C60323-28PVXC, CY7C60323-56LFXC and CY7C60333-56LFXC to CY7C60323-PVXC, CY7C60323-LFXC and CY7C60333-LFXC respectively Changed from Preliminary to final data sheet *B *C 461240 470485 See ECN See ECN TYJ TYJ *D 513713 See KKVTMP Change title from Wireless enCoRe II to enCoRe III Low Voltage Applied new template formatting Document #: 38-16018 Rev. *D Page 29 of 29 [+] Feedback |
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